Referring to FIG. 1, a block diagram illustrating a conventional phase-locked loop is shown. A conventional phase-locked loop (PLL) 10 is a feedback loop that includes a phase detector 14, which receives a reference clock 12 as one input, a charge pump (CP) 16, and a low pass filter 18 that provides a control voltage (VC) 20 to a voltage controlled oscillator (VCO) 22 for generation of an output clock 24. The clock 24 output by the VCO is feedback into the phase detector 14 through an optional divider 26, which frequency multiplies the output clock up.
The function of the PLL 10 is to lock the output of the VCO 20 to the phase of the reference clock 12. In operation, the phase detector 14 compares the phase of the incoming reference clock 12 with the divided frequency of the VCO output clock 24, and produces an output that is a function of the phase difference. This output from the phase detector 14 is used to control which direction the charge pump 16 charges/discharges the low pass filter 18 to produce a control voltage 20 frequency that has a reduced phase difference. The control voltage 20, in turn, controls the frequency of the VCO 22. This loop forms a negative feedback system. For the loop to achieve phase lock, the phase of the input reference clock 12 and the divided VCO output 24 must have a fixed phase relationship (ideally 0 degrees difference).
Temperature/process variations can cause problems for timing critical circuits, such as the PLL 10. To insure the PLL loop can null the effects of process/temperature changes, the control voltage 20 changes to control the VCO 22 frequency, and thus the output clock phase position, in such a way that this fixed phase relationship with the reference clock 12 is maintained. More particularly, as process/temperature drifts occur, the VC 20 changes in the direction that will yield zero phase difference between the input reference clock 12 and the divided VCO output 24. For example, a temperature change or slow process may slow down the VCO 22. In this case, the VC 20 voltage will need to move lower to speed up the VCO 22 and keep the loop locked (i.e., zero phase difference). However, although moving the VC 20 away from its center position helps insure the PLL loop will maintain lock, higher output clock jitter (i.e., unwanted phase movement) can result. Ideally, the control voltage 20 should operate within a particular voltage range for best output jitter performance.
Thus, it is desirable to both maintain PLL phase lock AND maintain the control voltage 20 at some predefined optimal voltage position for lowest jitter. Moreover, it would be desirable to have an error control signal that dynamically adjusts the voltage of the VCO 22 or other delay sensitive circuits/paths as the process/temperature changes.
Digital sampling or logic control may be implemented to account for process/temperature drift. For example, one approach utilizes a dual loop system where the PLL feedback acts as a fast loop and a slow loop is added to the PLL loop to slowly change the gain of the VCO 22 to keep the PLL loop running at the proper frequency. This slow loop only operates at power-up to determine the proper operating frequency.
Although digital sampling may account for process/temperature drift, it suffers several disadvantages. The main disadvantage of digital sampling is that it only works at power up to set the proper state of the regulator output, and there is only a limited number of output states that can be chosen to center the control voltage. This is done because it is undesirable to change the control voltage 20 with finite granularity as that will both cause abrupt changes in the output phase of the VCO 22, which is a source of jitter that needs to be avoided.
Accordingly, what is needed is a method and system for minimizing operational frequency limitations of a phase-locked loop by maintaining the control voltage at an optimal position as temperature/process changes occur during normal operation of the PLL. The present invention addresses such a need.